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Programmable Peripheral Interface (8255) ã The parallel input-output port chip 8255 is also called as programmable peripheral input-output port. The Intel’s 8255 is designed for use with Intel’s 8- bit, 16-bit and higher capability microprocessors. It has 24 input/output lines which may be individually programmed in two groups of twelve lines each, or three groups of eight lines. The two groups of I/O pins are named as Group A and Group B. Each of these two groups contains a subgroup of eight I/
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  Programmable Peripheral Interface (8255) ã The parallel input-output port chip 8255 is also called as programmable peripheralinput-output port. The Intel’s 8255 is designed for use with Intel’s 8- bit, 16-bit andhigher capability microprocessors. It has 24 input/output lines which may be individuallyprogrammed in two groups of twelve lines each, or three groups of eight lines. The twogroups of I/O pins are named as Group A and Group B. Each of these two groupscontains a subgroup of eight I/O lines called as 8-bit port and another subgroup of fourlines or a 4-bit port. Thus Group A contains an 8-bit port A along with a 4-bit port. Cupper. ã The port A lines are identified by symbols PA0-PA7 while the port C lines are identifiedas PC4-PC7. Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7and a 4-bit port C with lower bits PC0- PC3. The port C upper and port C lower can beused in combination as an 8-bit port C.ã Both the port C are assigned the same address. Thus one may have either three 8- bitI/O ports or two 8-bit and two 4-bit ports from 8255. All of these ports can functionindependently either as input or as output ports. This can be achieved by programmingthe bits of an internal register of 8255 called as control word register ( CWR ).ã The internal block diagram and the pin configuration of 8255 are shown in fig.ã The 8-bit data bus buffer is controlled by the read/write control logic. The read/writecontrol logic manages all of the internal and external transfers of both data and controlwords.ã RD, WR, A1, A0 and RESET are the inputs provided by the microprocessor to theREAD/ WRITE control logic of 8255. The 8-bit, 3-state bidirectional buffer is used tointerface the 8255 internal data bus with the external system data bus.ã This buffer receives or transmits data upon the execution of input or output instructionsby the microprocessor. The control words or status information is also transferredthrough the buffer.ã The signal description of 8255 are briefly presented as follows :ã PA7−PA0: These are eight port A lines that acts as either latched output or bufferedinput lines depending upon the control word loaded into the control word register.ã PC7−PC4 : Upper nibble of port C lines. They may act as either output latches orinput buffers lines.ã This port also can be used for generation of handshake lines in mode 1 or mode 2.ã PC3−PC0 : These are the lower port C lines, other details are the same as PC7−PC4lines.ã PB0−PB7 : These are the eight port B lines which are used as latched output lines orbuffered input lines in the same way as port A.ã RD : This is the input line driven by the microprocessor and should be low to indicateread operation to 8255.ã WR : This is an input line driven by the microprocessor. A low on this line indicateswrite operation.ã CS : This is a chip select line. If this line goes low, it enables the 8255 to respond to RDand WR signals, otherwise RD and WR signal are neglected.ã A1−A0 : These are the address input lines and are driven by the microprocessor.These lines A1-A0 with RD, WR and CS from the following operations for 8255.These address lines are used for addressing any one of the four registers, i.e. threeports and a control word register as given in table below.ã In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus, the  A0 and A1 pins of 8255 are connected with A1 and A2 respectively.ã D0−D7 : These are the data bus lines those carry data or control word to/from themicroprocessor.ã RESET : A logic high on this line clears the control word register of 8255. All ports areset as input ports by default after reset. Block Diagram of 8255 ã It has a 40 pins of 4 groups.1. Data bus buffer2. Read Write control logic3. Group A and Group B controls4. Port A, B and Cã Data bus buffer: This is a tristate bidirectional buffer used to interface the 8255 tosystem databus. Data is transmitted or received by the buffer on execution of input oroutput instruction by the CPU.ã Control word and status information are also transferred through this unit.ã Read/Write control logic: This unit accepts control signals ( RD, WR ) and alsoinputs from address bus and issues commands to individual group of control blocks (Group A, Group B).ã It has the following pins.a) CS – Chip select : A low on this PIN enables the communication between CPUand 8255.b) RD (Read) – A low on this pin enables the CPU to read the data in the ports orthe status word through data bus buffer.c) WR ( Write ) : A low on this pin, the CPU can write data on to the ports or on tothe control register through the data bus buffer.d) RESET: A high on this pin clears the control register and all ports are set to theinput modee) A0 and A1 ( Address pins ): These pins in conjunction with RD and WR pinscontrol the selection of one of the 3 ports.ã Group A and Group B controls : These block receive control from the CPU andissues commands to their respective ports.ã Group A - PA and PCU ( PC7 –PC4)ã Group B - PCL ( PC3 – PC0)ã Control word register can only be written into no read operation of the CW register isallowed.a) Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can beprogrammed in 3 modes – mode 0, mode 1, mode 2.b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can beprogrammed in mode 0, mode1.c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer.This port can be divided into two 4 bit ports and can be used as control signals forport A and port B. it can be programmed in mode 0.       Modes of Operation of 8255 ã There are two basic modes of operation of 8255. I/O mode and Bit Set-Reset mode(BSR).ã In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode onlyport C (PC0-PC7) can be used to set or reset its individual port bits.ã Under the I/O mode of operation, further there are three modes of operation of 8255,so as to support different types of applications, mode 0, mode 1 and mode 2.ã BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending onD0 of the control word. The bit to be set or reset is selected by bit select flags D3, D2and D1 of the CWR as given in table. ã I/O Modes : a) Mode 0 ( Basic I/O mode ): This mode is also called as basic input/output mode.This mode provides simple input and output capabilities using each of the threeports. Data can be simply read from and written to the input and output portsrespectively, after appropriate initialization.ã The salient features of this mode are as listed below:1. Two 8-bit ports ( port A and port B )and two 4-bit ports (port C upper and lower)are available. The two 4-bit ports can be combinedly used as a third 8-bit port.2. Any port can be used as an input or output port.3. Output ports are latched. Input ports are not latched.4. A maximum of four ports are available so that overall 16 I/O configuration arepossible.ã All these modes can be selected by programming a register internal to 8255 known asCWR.ã The control word register has two formats. The first format is valid for I/O modes ofoperation, i.e. modes 0, mode 1 and mode 2 while the second format is valid for bit set/ reset (BSR) mode of operation. b) Mode 1: ( Strobed input/output mode ) In this mode the handshaking control theinputand output action of the specified port. Port C lines PC0-PC2, provide strobe orhandshakelines for port B. This group which includes port B and PC0-PC2 is called as group B forStrobed data input/output. Port C lines PC3-PC5 provide strobe lines for port A. Thisgroup
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