# Combinational Logic Gate Design | Cmos | Electronic Circuits

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SEQUENTIAL LOGIC GATE DESIGN (LAB-6) INTRODUCTION TO VLSI DESIGN (ECE-467) FALL- 2013 UNIVERSITY OF ILLINOIS AT CHICAGO TA: VAHID FAROUTAN NAME: DEBOPAM DATTA UIN: 653501335 STUDENT: GRADUATE 1. Introduction: Sequential circuit designing is nothing but a combinatorial circuit working hand in hand with a memory element. The basic memory element can be implemented using two inverter loop. We have used that type of building Blocks. We have used the supply voltage of 2 volts for Static CMOS desi
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SEQUENTIAL LOGIC GATE DESIGN (LAB-6) INTRODUCTION TO VLSI DESIGN (ECE-467) FALL- 2013 UNIVERSITY OF ILLINOIS AT CHICAGO TA: VAHID FAROUTAN NAME: DEBOPAM DATTA UIN: 653501335 STUDENT: GRADUATE    1.   Introduction: Sequential circuit designing is nothing but a combinatorial circuit working hand in hand with a memory element. The basic memory element can be implemented using two inverter loop. We have used that type of building Blocks. We have used the supply voltage of 2 volts for Static CMOS design and minimum feature size (aspect ratio) of (250nm/250nm). The technology file we have used ‘ mitll_fdsoi ’ whi ch is a low power CMOS process. 2.   Organisation: 1.   Design Theory 2.   Circuit Topology and structure 3.   Layout Samples of Positive Edge triggered D-Flip flop and other Design Process 4.   Parasitic extraction and display 5.   Circuit Response i) Without parasitic ii) With Parasitic. 6.   Discussion 3.   Design Theory: As per the problem statement we have to design a positive edge triggered master-slave D-flip flop. The Truth Table for D- Flip Flop is shown below. The master slave configuration works in an alternative way when Master is transparent to its Input the slave is latched and vice versa. So though the D-Flip Flops are Level triggered implementation of this configuration makes the whole circuit behave as an edge triggered. We have used a two inverter Loop with the Transmission gate switch topology to implement Level triggered D-flip flop. The inverters have a PMOS/NMOS aspect ratio of 3 and the pass transistor have a PMOS/NMOS aspect ratio of 1. We have sacrificed the standard CMOS design to reduce the number of Transistor count. For General NAND based design the transistor count is 28. But for our design the number of count is only 16. The problem statement had a restriction of 10GHz operating clock but we had designed the circuit to operate it in 5GHz ideally and 0.8GHz practically.    4.   CIRCUIT TOPOLOGY:   FIG-1: Schematic of the used circuit FIG-2: Schematic of Pass Transistor   FIG-3: Schematic of the Inverter         Symbol Generation: FIG-4: Symbol of the Generated D Flip Flop    Test Bench circuit : FIG-5: Test bench circuit
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