Investigation of Pillar Thickness Variation Effect on Oblique Rotating Implantation (ORI)-Based Vertical Double Gate MOSFET

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Microelectronics Journal 41 (2010) 827–833 Contents lists available at ScienceDirect Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo Investigation of pillar thickness variation effect on oblique rotating implantation (ORI)-based vertical double gate MOSFET Munawar A. Riyadi a,b,n, Ismail Saad c, Razali Ismail a a Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Malaysia Department of Electrical Engineering, Diponegoro University, Semaran
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  Investigation of pillar thickness variation effect on oblique rotatingimplantation (ORI)-based vertical double gate MOSFET Munawar A. Riyadi a,b, n , Ismail Saad c , Razali Ismail a a Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Malaysia b Department of Electrical Engineering, Diponegoro University, Semarang 50271, Indonesia c School of Engineering & IT, Universiti Malaysia Sabah, 88999 Kota Kinabalu, Malaysia a r t i c l e i n f o  Article history: Received 11 November 2009Received in revised form9 July 2010Accepted 12 July 2010Available online 22 July 2010 Keywords: Vertical MOSFETOblique rotating ion implantationDouble gateSilicon thickness effectFully depleted a b s t r a c t The rapid scaling of integrated circuit requires further shrinkage of lateral device dimension, whichcorrelates with pillar thickness in vertical structure. This paper investigates the effect of pillar thicknessvariation on vertical double gate MOSFET (VDGM) fabricated using oblique rotating ion implantation(ORI) method. For this purpose, several scenarios of silicon pillar thickness t  si were evaluated for20–100 nm channel length. The source region was found to merge at pillar thickness below 75 nm, whichresults in floating body effect and creates isolated region in the middle of pillar. The vertical devices usingORI method show better performance than those with conventional implantation method for all pillarthickness, due to the elimination of corner effect that degrades the gate control. The presence of isolateddepletion region in the middle of pillar at floating body increases parasitic effect for higher drainpotential. By further reduction of pillar thickness towards fully depleted feature, the increase in gate-togate charge coupling improves the performance of ORI-based vertical double gate MOSFET, as evident innear-ideal swing value and lower DIBL, compared to the partially depleted and body-tied device. & 2010 Elsevier Ltd. All rights reserved. 1. Introduction Recent development of integrated circuit reveals that severalfabrication aspects are already approaching the limit, especiallywhen the dimensions are of nanometer scale[1,2]. Furthermore,the complexity of lithography for nanoscale technology posesmajor technological challenge and skyrocketing manufacturinginvestment[3]. In dealing with this issue, some innovativestructures for further scaling of nanoscale devices have beenelaborated, and the vertical metal oxide semiconductor field effecttransistor (MOSFET) is identified as one of them[4,5]. The benefitsof applying vertical structure in the nanoscale era have beenpromoted by a number of researchers, e.g.[6–13]. For ultra shortchannel length, the channel region could be produced withrelaxed lithography in vertical architecture, instead of usingcomplicated lithography tools for planar structure. It can handlethe lithography-bounded problem in further scaling by convertingthe lithography process into layer definition/deposition processfor adjusting the channel length. Moreover, as the active area islocated at the silicon pillar sidewall, it is easier to produce doubleor multiple gate structure on vertical geometry that subsequentlyincreases the drive current, with self-aligned features for bothgates, which are difficult to obtain in planar geometry. It also hasa possibility to increase the space density[8], depending on theapplication, especially for layout with different W  / L ratios. Inplanar MOSFET, the design of various W  / L will directly result inthe different size of each transistor, expanding the occupied area.But in vertical structure, the variation of  W  / L , and particularly thegate length, can be adjusted in the vertical direction by specificprocess, while maintaining the width of pillar.Various methods have been proposed for developing nanometer-sized vertical structure. A number of fabrication techniques havebeen elaborated, either by layer epitaxy[9–11]or by silicon pillaretch combined with ion implantation methods[12–16]. Epitaxymethod seems to be an easier way to define the channel regionvertically, but it faces difficulties in manufacturing for differenttypes of grown layer in n- and p-type MOS. Conventional ionimplantation method allows the CMOS-compatible processing;however, the formation of direct vertical channel at sidewall waslimited by either the silicon pillar height itself or by the nitridespacer thickness that is applied as a mask for sidewall region,which eventually creates L-shaped channel (Fig. 1(a)). This shapeof channel leads to corner effect in the bottom of pillar, whicheventually degrades the device’s performance[17]. Moreover,parasitic overlap capacitance problem in source/drain-to-gatearea is commonly found in vertical structure that providesdrawback effect on the switching speed. The use of fillet localoxidation (FILOX) technique above source/drain region was Contents lists available atScienceDirectjournal homepage:www.elsevier.com/locate/mejo Microelectronics Journal 0026-2692/$-see front matter & 2010 Elsevier Ltd. All rights reserved.doi:10.1016/j.mejo.2010.07.004 n Corresponding author at: Faculty of Electrical Engineering, Universiti TeknologiMalaysia, 81310 Skudai, Johor, Malaysia. Tel.: +60 7 5536266;fax: +60 7 5566272. E-mail addresses: munawar.riyadi@gmail.com,munawar.riyadi@ieee.org(M.A. Riyadi).Microelectronics Journal 41 (2010) 827–833  introduced to reduce the problem[18]. Subsequently this work wasenhanced by others such as incorporating dielectric pocket[19]orintroducing ORI method[20]. Applying dielectric pocket may reduceshort channel effect, but the possibility of further shrinkage in pillardimension is very limited due to the presence of dielectric in themiddle of pillar’s top area. The later, combined with FILOX technique,was convincingly improving the channel scaling with straightvertical current (as illustrated inFig. 1(b)) while keeping theparasitic capacitance low and offers good short channel effectcontrol. However, the pillar thickness in previous report isnoticeably large, and its pillar shrinkage effect has not beenelaborated further. In the trend of increased density for overallchip, the pillar width tends to be made in smaller dimension; thus itis of importance to investigate the effect of pillar thickness variation,especially on the fully depleted case.In this paper, the effect of silicon pillar thickness variation onvertical double gate MOSFET with FILOX and ORI method isinvestigated numerically. The effect of processing variation iselaborated as well as the possibility of formation of partially andfully depleted device using this method, as an extension of aprevious work. The device’s electrical characteristic and itsrespective subthreshold behaviour are also elaborated to under-stand the deviceperformances,especiallyinthe veryshortchannel. 2. Device simulation The proposed vertical MOSFET structure has the feature of symmetrical self-aligned source/drain region for both gates andexhibits straight vertical channel on the sidewall, as shown inFig. 1(b). The ORI method is employed to reveal this uniquefeature of the device structure. A o 1 0 0 4 silicon wafer withuniform boron doping of 1 Â 10 19 cm À 3 is selected as the basesubstrate. This relatively high substrate doping gives a benefit forthe suppression of short channel effect[21]. The silicon pillar isformed by dry etch of substrate, which is selectively covered bynitride as etch mask, with the width of nitride equal to the pillarthickness t  si . In addition, the channel length definition is affectedby h  pillar  , the height of pillar (Fig. 2(a)). Stress relief oxide of 20 nmis thermally grown over all silicon surface, followed by thedeposition of nitride layer, which subsequently is dry-etchedanisotropically to define the active area (Fig. 2(b)). Later, athermal oxidation process is held to produce FILOX in the areawhich is not protected by the nitride spacers; those are the wholeactive area and the top of the pillar (Fig. 2(c)).The self-aligned source and drain region are constructed byarsenic implantation (6 Â 10 15 cm 2 , 150 keV) using oblique rotat-ing implantation (ORI) method[20](Fig. 2(d)). This method has shown a better shape of source region in the bottom, with thedrain-to-source current flowing in pure vertical direction[20],rather than with the non-ORI method. After etching of nitridespacers and stress relief oxide underneath, a 3 nm silicon oxidelayer is grown on the sidewall of pillar as a gate dielectric. Later,polysilicon with in-situ As doping is deposited for gate electrode.Polysilicon spacer is patterned using dry etch, forming a doublegate structure with self-aligned features (Fig. 2(e)). After deposi-tion of LTO for isolation, rapid thermal annealing (RTA, 1100 1 C,10 s) is carried out for dopant activation. Following the contactopening process, aluminum is deposited as metal contact at gate,source and drain (Fig. 2(f), while contact for the double gate is notshown here).The electrical characteristics of the device were obtained bysimulating the final structure using Silvaco’s Atlas softwarepackage[22]. The drift–diffusion (DD) transport model with theBoltzmann carrier transport framework was used, as it is able topredict I  – V  characteristics of DG-MOSFET[23]. Even for nanoscale Fig. 1. Possible channel formation in vertical MOSFET: (a) L-shape channel in the corner and (b) direct (pure) vertical current channel. Fig. 2. Process flow for vertical double gate fabrication: (a) pillar definition,(b) nitride spacer, (c) FILOX formation, (d) source/drain implant using ORI (45 1 tiltand 180 1 rotation), (e) poly-gate formation and (f) metal contact. M.A. Riyadi et al. / Microelectronics Journal 41 (2010) 827–833 828  size 4 10 nm, Granzner et al.[24]have shown that forDG-MOSFET’s current characteristics, the DD and Monte-Carlosimulation results produced excellent agreement, while Ren andLundstorm[25]and Rhew and Lundstorm[26]have revealed that the DD model can predict I  – V  characteristics of short-channelMOS devices more realistically than the energy-balance (EB)model. It is then combined with Lombardi CVT model[27]whereits semi-empirical equation gave the complete correlationbetween carrier concentration, carrier mobility, electric field andtemperature for non-planar device, which is the vertical device,while Shockley–Read–Hall (SRH) recombination with fixed carrierlifetimes models was selected. Moreover, the combination of Gummel and Newton numerical methods was employed forsolving quantities for obtaining a convergence of the devicestructure.The process simulation was validated by comparing thesimulated and experimental results from[14]of the 125 nmchannel length vertical structure fabricated without the ORImethod, as shown inFig. 3. The figure shows good agreementbetweenthe simulated and experimental results. The discrepanciesof subthreshold current from the comparison show that thesimulation gives lower drain current than the experimental datawith maximum of an order of magnitude at around V   g  ¼ 1.5 V,which may result from the additional processes not sufficientlyexplained in[14]. However, the extraction of threshold voltage forboth data indicates a similar value, which is an indication that thesimulation process and the parameters used in the simulation are justified.For the purpose of investigating the channel and junctiondepth caused by variation of pillar dimension, the siliconthickness and height were varied. Several devices with channellength from 20 to 100 nm at various silicon thicknesses t  si (25–75 nm) were constructed and simulated. The values of pillarthickness are selected as representatives of different bodypotential scenarios in the pillar. The conventional verticalMOSFET, which employs the conventional implantation method,was used as a comparison for several pillar thicknesses. However,the channel length for conventional vertical MOSFET is limited to50–100 nm due to recessed channel length in lateral direction atthe bottom of pillar that is around 20–40 nm in length, whichwere also counted here as a part of L-shaped channel length,which in turn makes it difficult to obtain very short channelstructure. In all cases, the drain is always on top of the pillar, andthe backside substrate is connected to the ground. 3. Pillar thickness variation and junction profile Fig. 4shows the cross-section of devices with two differentpillar thicknesses with different channels and source profiles( t  si ¼ 75 and 46 nm, with L ch ¼ 40 and 70 nm, respectively, for V  ds ¼ 0.1 V and V   gs ¼ 1 V) after all processing sequences werecompletely done. In addition, the vertical cross-section of the75 nm thick pillar (Fig. 5) reveals the ability of ORI-based processto obtain the pure vertical channel, as opposed to the non-ORI forthe same pillar thickness. The current direction in channel area ispurely vertical from drain to source for both cases, as the result of  Fig. 3. Comparison between simulation model and experimental data (taken from[14]) for L ch ¼ 125 nm, double gate structure and pillar width ¼ 9 m m. Fig. 4. Cross-section of vertical DG-MOSFET structure with ORI method, taken at V   gs ¼ 1 V and V  ds ¼ 0.1 V for: (a) t  si ¼ 75 nm, L ch ¼ 50 nm and (b) t  si ¼ 45 nm, L ch ¼ 100 nm. M.A. Riyadi et al. / Microelectronics Journal 41 (2010) 827–833 829  the source region overlapping the corner side of pillar in thebottom area. This feature is of a great advantage in applying ORImethod; with conventional implantation technique it is likelythat the channel area becomes L-shape, which is the case of somereported devices (e.g.[7,14,28]) as a consequence that theimplanted doping for source region cannot occupy the pillar’scorner at the bottom.But the junction profile inside the pillar changes its shapewhen the pillar is made thinner, according to the source regionboundary in relation with the pillar’s corner. For device with t  si ¼ 75 nm (Fig. 4(a)), the source regions at the right and left sideare separately formed, and the pillar region’s channel area is tiedto the substrate. The channel region is connected to and has thesame potential with substrate, similar to bulk transistor. Mean-while, while smaller pillar thickness is chosen ( t  si ¼ 46 nm forFig. 4(b)), both source parts will eventually join together and forma single region, thus the pillar region becoming disconnected fromsubstrate. Thus, for lower thickness, the pillar region is separatedfrom substrate by the source region and is not tied to anypotential, and floating body is created. This floating body in turncould be a disadvantage for the device performance, as it mayreduce the output resistance and create parasitic transistor on it,which is the case in the partially depleted SOI MOS[29]. Thetransition width between body-tied and floating body of channelarea in pillar depends on several factors, e.g. implantation doses,dielectric thickness and substrate doping, which require optimi-zation for distinct process recipes. In this research, we found thatthe floating body occurs for pillar thickness below 75 nm, andpartially depleted channel is formed. Moreover, when thethickness of the pillar is made thinner, less than 25 nm, it turnsout to be fully depleted.The electron–hole concentration and potential distributionalong the channel, taken for V   gs ¼ 1 V and V  ds ¼ 0.1 V, are shown inFig. 6. At t  si ¼ 57 nm, majority carriers in the middle of pillarregion are holes, with almost as many concentration ( $ 10 18 –10 19 cm À 3 ) as those at the pillar’s substrate, which has the sametype of impurity (p-type). The collection of carriers in the middlearea of pillar creates an island (as big as 50 nm in diameter at L ch ¼ 100 nm) surrounded by the region whose majority carrier isalready depleted; some literatures call this island as ‘‘depletionisolation’’ region[30]. In decreased pillar thickness, the depletionisolation size as well as its peak carrier concentration are reduced.Furthermore, at t  si ¼ 46 nm, the hole concentration in the pillar’smiddle region is overpowered by electron (10 7 –10 12 cm À 3 ), whilein t  si ¼ 36 nm, the electron concentration has almost the similarconcentration with the initial substrate impurities in many partsof the pillar. In addition, the depletion isolation is undetectedfrom the graph for this thickness, while the potential barrierbetween drain and source exhibits a very low barrier created atthe lowest t  si . Moreover, the behaviour at pillar thickness of 25 nm (not shown) represents the condition of fully depleteddevice, as is noted by the calculation of depletion width w d for therespective pillar thickness[31]. This low potential barrier explainsthe high current drive capability on lower pillar thickness, inwhich the carriers flow easily without significant barrier when thechannel starts conducting. 4. Result and discussion The electrical performance for different channel lengths from100 to 20 nm is analyzed for several pillar thicknesses.The threshold voltage for both vertical conventional and ORIDG-MOSFET becomes smaller in shorter channel length due tocharge sharing increase between source and drain terminals andalso electric field build-up at the source, which reduces channelregion controllability by the gate. In addition, the vertical ORIMOSFET shows lower threshold voltage than its conventionalcounterpart at every channel length for particular pillar thick-nesses (Fig. 7), which is the direct result of straight channelgeometry. The conventional vertical structure (with the L-shapechannel) lacked the gate control in the corner region, also knownas ‘‘corner effects’’, which made the decreased potential in thecorner area compared to the straight channel, thus preventing thequick conversion into inversion and requiring higher thresholdvoltage. The similar phenomenon is also found in grooved channelin planar MOSFET, as has been elaborated in[32,33]. In addition,the lower threshold is advantageous for the concern of powerconsumption in conduction state. The threshold voltage decreaseis observed on shorter channel for both structures but withtendency of more rapid decline for L-shaped channel, which needto be avoided for better short channel effect control.The pillar thickness variation effect on drain induced barrierlowering (DIBL) is shown inFig. 8. The DIBL is calculated forthreshold voltages taken at V  D ¼ 0.1 V and 1.0 V, by the formula:DIBL  ¼ V  T  at V  D ¼ 0 : 1 V À V  T  at V  D ¼ 1 : 0 V = 1 : 0-0 : 1 ð Þ in mV/V. For each pillarthickness, it is found that the shorter the channel length, thehigher the DIBL, as expected. The pattern is found for both ORIand conventional vertical DG-MOSFET, but the ORI-based verticalDG MOSFETs tend to get lower DIBL in shorter channel than the Fig. 5. The cross-section in vertical pillar of 75 nm shows the formation of directchannel in vertical direction for ORI method as opposed to the non-ORI method. Fig. 6. The concentration of electron and hole in cross-sectional area A–A 0 of Fig. 4(b) for several pillar thicknesses ( L ch ¼ 100 nm), for V  ds ¼ 0.1 V and V   gs ¼ 1 V. M.A. Riyadi et al. / Microelectronics Journal 41 (2010) 827–833 830
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