Itanium Processor SLIDES1

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1 ITANIUM PROCESSOR *CONTENTS* ã INTRODUCTION ã TODAY’S ARCHITECTURE CHALLENGES ã IA-64 ARCHITECTURE PERFORMANCE FEATURES ã IA-64 SYSTEM ENVIRONMENT ã BENEFITS OF ITANIUM PROCESSOR ã INTEL ITANIUM 2 PROCESSOR ã APPLICATIONS ã FUTURE SCOPE ã SUMMARY ã CONCLUSION 2 INTRODUCTION The Itanium processor family came about for several reasons, but the primary one was that the processor architecture advances of RISC were no longer growing at the rate seen in the 1980’s or the 1990’s.Yet,customers con
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  ITANIUM PROCESSOR *CONTENTS* ã INTRODUCTION ã TODAY’S ARCHITECTURE CHALLENGES ã IA-64 ARCHITECTURE PERFORMANCE FEATURES ã IA-64 SYSTEM ENVIRONMENT ã BENEFITS OF ITANIUM PROCESSOR  ã INTEL ITANIUM 2 PROCESSOR  ã APPLICATIONS ã FUTURE SCOPE ã SUMMARY ã CONCLUSION 1  INTRODUCTION The Itanium processor family came about for several reasons, but the primary one was that the processor architecture advances of RISCwere no longer growing at the rate seen in the 1980’s or the1990’s.Yet,customers continued demand greater application performance. The Itanium processor family was developed as a response toaddress the future performance and growth needs of business, technical andscientific users with greater flexibility, better performance and a muchgreater ‘bang for the buck’ in the price performance arena. Itanium is thefirst processor to use EPIC(Explicit Parallel Instruction Computing)architecture. Its performance is to be better than the present day ReducedInstruction Set Computing and Complex Instruction Set Computing(RISC &CISC).The Itanium architecture achieves a more difficult goal than a processor that could have been designed with ‘price as no object’. Rather, itdelivers near-peerless speed at a price that is sustainable by the mainstreamcorporate market. 2  TODAY’S ARCHITECTURE CHALLENGES The main challenges in today’s architecture are the following: ã Sequential Semantics of the ISA ã Low Instruction Level Parallelism(ILP) ã Unpredictable Branches, Memory dependencies ã Ever Increasing Memory Latency, Ever increasing Memory ã Limited Resources(registers,memoy address) ã Procedure call,Loop pipelining Overhead IA-64 ARCHITECTURE PERFORMANCE FEATURES ã Explicitly Parallel Instruction Semantics ã Predication ã Control/Data Speculation ã Massive Resources(registers,memory) ã Register Stack and its Engine ã Memory Hierarchy Management Support ã Software Pipelining Support 3  EXPLICITLY PARALLEL INSTRUCTION SEMANTICS  Dependent Independentadd r1=r2,r3 ;; add r1=r2,r3sub r4=r1,r2 ;; sub r4=r11,r2shl r5=r4,r8 ;; shl r5=r14,r8  PREDICATION  As a result of predication unpredictable branches are removed.Execution is based on a previously determined condition.Proper use of this facilityremoves many problems in today’s IA-32 architecture.Predication .can beconsidered as the greatest aspect of IA-64’s design. CONTROL SPECULATION  Code speculation is defined by the Intel as the compiler concept “ControlSpeculation” where “an instruction or a sequence of instructions is executed before it is known that the dynamic control flow of the program will actuallyreach the point in the program where the sequence of instructions is needed”.  DATA SPECULATION  Data Speculation is defined by Intel as “a sequence of instructions whichconsist of an advanced load,zero or more instructions dependent on the valueof that load, and a check instruction” which serves to validate whether or notthe speculation was successful.  RSE  Automatically call store/restores registers without software intervension.Provides illusion of infinite physical registers.  MASSIVE MEMORY RESOURCES  ã 8 billion GB accessible ã Both 64-bit and 32-bit pointers are supported ã Both Little Endian and Big Endian order are supported .4
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